One type of prior art flash Erasable and electrically Programmable Read-Only Memory ("flash EPROM") is organized into rows and columns. Memory cells are placed at intersections of word lines and bit lines. Each word line is connected to the gates of a plurality of memory cells in one row. Each bit line is connected to the drains of a plurality of memory cells in one column. The sources of all the memory cells are connected to a common source line. FIG. 1 shows the above-described array configuration of a prior art flash EPROM.
The flash EPROM can be programmed by a user, and once programmed, the flash EPROM retains its data until erased. When programmed, the flash EPROM is programmed byte by byte or word by word. Once programmed, the entire contents of the flash EPROM can be erased by electrical erasure in one relatively rapid operation. A high erasing voltage is made available to the sources of all the cells in the flash EPROM simultaneously. This results in a full array erasure. The flash EPROM may then be reprogrammed with new data.
One disadvantage of this prior flash EPROM structure is the characteristics of array erasure. When changes are sought to be made to a program stored in the array, the entire array must be erased and the entire program be rewritten into the array, even when the changes are minor.
One prior approach to solving this problem is to reorganize the array into blocks so that the high erasing voltage is made available only to the source of every cell within one block to be erased. By this arrangement, only a block of the memory array is erased, rather than having the entire memory array erased.
One disadvantage of this prior approach is that interference can arise from the blocked array configuration of the flash EPROM. This interference can be of two types. One type is referred to as drain disturbance. Drain disturbance arises when the drains of cells along a column are interconnected across a block boundary. Another type of interference is referred to as gate disturbance. Gate disturbance arises when the gates of cells along a row are interconnected across a block boundary.
An example of "gate disturbance" is as follows. A prior flash EPROM is divided into "bit line blocks" by organizing bit lines into groups. During programming of the flash EPROM, a high voltage V.sub.pp (typically 12 volts) is applied to the control gate of a selected cell in a selected block through a selected word line. A program voltage V.sub.P (typically 7 volts) lower than V.sub.PP is applied to the drain of the selected cell through a selected bit line. The sources of all the cells within the selected block are grounded during the operation. The gates of unselected cells along unselected word lines both in the selected block and unselected blocks are grounded. The drains of unselected cells along unselected bit lines both in the selected block and unselected blocks are either left floating or grounded.
In this situation, the unselected cells along the selected word line will have the high positive voltage V.sub.PP (i.e., 12 volts) coupled to their floating gates. An electric field is thus present across each of the unselected cells along the selected word line. The presence of the electric field across each of the unselected cells can cause movement of electrons to the floating gates. This increases the threshold of these unselected cells, causing those unselected cells to be slowly programmed. This is referred to as slow programming. Thus, gate disturbance can result in unwanted slow programming.
An example of "drain disturbance" is as follows. A prior flash EPROM is divided into "word line blocks" by organizing word lines into groups. During programming of the flash EPROM, a high voltage V.sub.PP of 12 volts is applied to the control gate of a selected cell in a select block through a selected word line. A program voltage V.sub.P of 7 volts is applied to the drain of the selected cell through a selected bit line. The drain of unselected cells along the selected bit line both in the selected block and unselected blocks will be coupled to the voltage V.sub.P of 7 volts. The gates of the unselected cells will be grounded. This creates an electric field across each of the unselected cells along the selected bit line, which causes unwanted movement of electrons from the floating gate to the drain. Thus the threshold of each of the unselected cells is decreased by unwanted movement of electrons, causing those unselected cells to be slowly erased. This is referred to as slow erasing. Thus, drain disturbance can result in unwanted slow erasing.
"Gate disturbance" and "drain disturbance" are especially pernicious because their effects accumulate as either programming or erasing of a selected block of a flash EPROM is repeated. Unwanted movement of electrons in certain unselected cells happens each time there is a programming or erasure operation.
For gate disturbance, the thresholds of unselected cells keep increasing, and the unselected cells are slowly programmed. For drain disturbance, the thresholds of unselected cells keep decreasing, and the unselected cells are slowly erased. If the accumulated gate or drain disturbances reach a certain degree on an unselected cell, the state of the unselected cell can be completely altered. In other words, an unselected cell could be unintentionally programmed or erased over time.